Registered AXI4-Stream Interfaces - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

As a default, AXI4-Stream interfaces are always implemented as registered interfaces to ensure that no combinational feedback paths are created when multiple HLS IP blocks with AXI4-Stream interfaces are integrated into a larger design. For AXI4-Stream interfaces, four types of register modes are provided to control how the interface registers are implemented:

Only the TDATA and TVALID signals are registered.
Only the TREADY signal is registered.
All signals (TDATA, TREADY, and TVALID) are registered. This is the default.
None of the port signals are registered.

The AXI4-Stream side-channel signals are considered to be data signals and are registered whenever TDATA is registered.

There are two basic methods to use an AXI4-Stream in your design:

  • Use an AXI4-Stream without side-channels.
  • Use an AXI4-Stream with side-channels.

This second use model provides additional functionality, allowing the optional side-channels which are part of the AXI4-Stream standard, to be used directly in your C/C++ code.