Operator Configuration - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

The syn.op command lets you configure the default implementation style, latency, and precision for different operators used for the HLS component. You can add multiple syn.op commands to a config file to specify the details of different operators. If an operator is not specified then the tool determines the default values for the component.

You can override the default settings specified by the syn.op command by using the syn.directive.bind_op command for specific variables.

The syntax for the syn.op command is as follows:
syn.op=op:mul impl:dsp
syn.op=op:add impl:fabric latency:6
syn.op=op:fmacc precision:high
syn.op=op:hdiv latency:5
  • syn.op=: Starts the command
  • op:<operator>: Specifies the op keyword followed by the operator being defined. The supported operators include:
    • mul: integer multiplication operation

    • add: integer add operation

    • sub: integer subtraction operation

    • fadd: single precision floating-point add operation

    • fsub: single precision floating-point subtraction operation

    • fdiv: single precision floating-point divide operation

    • fexp: single precision floating-point exponential operation

    • flog: single precision floating-point logarithmic operation

    • fmul: single precision floating-point multiplication operation

    • frsqrt: single precision floating-point reciprocal square root operation

    • frecip: single precision floating-point reciprocal operation

    • fsqrt: single precision floating-point square root operation

    • dadd: double precision floating-point add operation

    • dsub: double precision floating-point subtraction operation

    • ddiv: double precision floating-point divide operation

    • dexp: double precision floating-point exponential operation

    • dlog: double precision floating-point logarithmic operation

    • dmul: double precision floating-point multiplication operation

    • drsqrt: double precision floating-point reciprocal square root operation

    • drecip: double precision floating-point reciprocal operation

    • dsqrt: double precision floating-point square root operation

    • hadd: half precision floating-point add operation

    • hsub: half precision floating-point subtraction operation

    • hdiv: half precision floating-point divide operation

    • hmul: half precision floating-point multiplication operation

    • hsqrt: half precision floating-point square root operation

    • facc: single precision floating-point accumulate operation

    • fmacc: single precision floating-point multiply-accumulate operation

    • fmadd: single precision floating-point multiply-add operation

    Tip: Comparison operators, such as dcmp, are implemented in LUTs and cannot be implemented outside of the fabric, or mapped to DSPs, and so are not configurable with the syn.op or syn.directive.bind_op commands.
  • impl:<value>: Specifies the implementation (impl) keyword followed by the value for the specified operator. When impl is not specified, the default is for the tool to determine the best implementation for a given operator. Supported values include:
    • all: All implementations. This is the default setting.

    • dsp: Use DSP resources

    • fabric: Use non-DSP resources

    • meddsp: Floating Point IP Medium Usage of DSP resources

    • fulldsp: Floating Point IP Full Usage of DSP resources

    • maxdsp: Floating Point IP Max Usage of DSP resources

    • primitivedsp: Floating Point IP Primitive Usage of DSP resources

    • auto: enable inference of combined facc | fmacc | fmadd operators

    • none: disable inference of combined facc | fmacc | fmadd operators

  • latency:<value>: Specifies the latency keyword followed by the value. Defines the default latency for the binding of the operator to the implementation resource. The valid value range varies for each implementation (impl) of the operation. The default is -1, which lets the tool apply the standard latency for the implementation resource.
    Tip: You can specify the latency for a specific operation without specifying the implementation. This leaves the tool free to choose the implementation while managing the latency.
  • precision:<value>: Used for floating point operators (facc, fmacc, and fmadd), this specifies the precision keyword followed by one of the following:
    • low: Use a low precision (60 bit and 100 bit integer) accumulation implementation when available. This option is only available on certain non-AMD Versalâ„¢ devices, and can cause RTL/Co-Sim mismatches due to insufficient precision with respect to C++ simulation. However, it can always be pipelined with an II=1 without source code changes, though it uses approximately 3X the resources of standard precision floating point accumulation.
    • high: Use high precision (one extra bit) fused multiply-add implementation when available. This option is useful for high-precision applications and is very efficient on Versal devices, although it can cause RTL/Co-Sim mismatches due to the extra precision with respect to C++ simulation. It uses more resources than standard precision floating point accumulation.
    • standard: standard precision floating point accumulation and multiply-add is suitable for most uses of floating-point, and is the default setting. It always uses a true floating-point accumulator that can be pipelined with II=1 on Versal devices, and II that is typically between 3 and 5 (depending on clock frequency and target device) on non-Versal devices.