Memory Mapped Interfaces - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

As mentioned earlier, Vitis HLS allows the user to specify M_AXI interfaces for arrays in the interface. Since this memory is off-chip and not local, access to these memories can be expensive in terms of cycles. To optimize how these accesses are made, Vitis HLS performs an automatic burst optimization, to efficiently read/write to these external memories. Bursting is an optimization that tries to intelligently aggregate the memory accesses to the DDR to maximize the throughput bandwidth and/or minimize the latency. Bursting is one of many possible optimizations to the kernel. Bursting typically gives you a 4-5x improvement. Bursting is useful when you have contention on the DDR ports from multiple competing kernels.

For more information on this bursting optimization and details on how to write code to infer more bursts, please review the Optimizing AXI System Performance section.