Introduction to Interface Synthesis - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

The arguments of the top-level function in an HLS component are synthesized into interfaces and ports that group multiple signals to define the communication protocol between the HLS component and elements external to the design. The tool defines interfaces automatically, using industry standards to specify the protocol used. The type of interfaces that the tool chooses depends on the data type and direction of the parameters of the top-level function, the target flow for the HLS component, the default interface configuration settings as described in Interface Configuration, and any specified INTERFACE pragmas or directives.

Tip: Interfaces can be manually assigned using the INTERFACE pragma or directive. Refer to Adding Pragmas and Directives for more information.
The target flows supported for an HLS component include the following as described in Target Flow Overview:
  • The AMD Vivado™ IP flow which is the default flow for the tool
  • The Vitis Kernel flow, which is the bottom-up design flow for the Vitis Application Acceleration Development flow

You can specify the target flow when creatingan HLS component as described in Creating Vitis HLS Components.

The interface defines three elements of the kernel:
  1. The interface defines channels for data to flow into or out of the HLS design. Data can flow from a variety of sources external to the kernel or IP, such as a host application, an external camera or sensor, or from another kernel or IP implemented on the AMD device. The default channels for Vitis kernels are AXI adapters as described in Interfaces for Vitis Kernel Flow.
  2. The interface defines the port protocol that is used to control the flow of data through the data channel, defining when the data is valid and can be read or can be written, as defined in Port-Level Protocols for Vivado IP Flow.
    Tip: These port protocols can be customized in the Vivado IP flow, but are set and cannot be changed in the Vitis kernel flow, in most cases.
  3. The interface also defines the execution control scheme for the HLS design, specifying the operation of the kernel or IP as pipelined or sequential, as defined in Block-Level Control Protocols.

As described in Best Practices for Designing with M_AXI Interfaces the choice and configuration of interfaces is a key to the success of your design. However, the tool tries to simplify the process by selecting default interfaces for the target flows as described above.

After synthesis completes you can review the mapping of the software arguments of your C/C++ code to hardware ports or interfaces in the SW I/O Information section of the Synthesis Summary report.