The default settings of the tool vary between the Vivado IP flow and the Vitis Kernel flow. The following table shows the default settings of both flows so that you can quickly determine the differences in the default configuration.
Configuration | Vivado | Vitis |
---|---|---|
clock_uncertainty | 27% | 27% |
syn.compile.pipeline_loops | 64 | 64 |
syn.compile.name_max_length | 255 | 255 |
vivado.optimization_level | 0 | 0 |
vivado.phys_opt | none | none |
syn.rtl.module_auto_prefix | true | true |
syn.rtl.register_reset_num | 0 | 3 |
syn.schedule.enable_dsp_full_reg | true | true |
syn.directive.interface | IP mode | Kernel mode |
syn.interface.m_axi_addr64 | true | true |
syn.interface.m_axi_latency | 0 | 64 |
syn.interface.m_axi_alignment_byte_size | 1 | 64 |
syn.interface.m_axi_max_widen_bitwidth | 0 | 512 |
syn.interface.default_slave_interface | s_axilite | s_axilite |
syn.interface.m_axi_offset | slave | slave |
Beyond these default settings, you must also package the generated RTL files
for use in downstream processes, such as Vivado designs
integrating multiple RTL files or Vivado IP into a single
design. Or a Vitis kernel integrated with other PL
kernels and an AI Engine graph
application in a System project. The generated output is determined by the package.output.format
and package.output.syn
settings, as described in Packaging the RTL Design. The output format lets you create a packaged format
from the RTL files of the design. The default output format is the Vivado IP .zip
file format, which can be
added to your IP catalog, and used in Vivado IP
integrator features. You can also specify the output format as XO format to package the
RTL files as a kernel for use in the Vitis development
flow. The selection of flow_target
does not
automatically specify the output format. You must do this yourself.