Dataflow Viewer - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
Release Date
2023.2 English
The DATAFLOW optimization is a dynamic optimization which can only be fully understood after RTL Co-simulation is complete. Due to this fact, after C synthesis the Dataflow viewer lets you see the dataflow structure inferred by the tool, inspect the channels (FIFO/PIPO), and examine the effect of channel depth on performance. Performance data is back-annotated to the Dataflow viewer after co-simulation.
Important: You can open the Dataflow viewer without running RTL co-simulation, but your view will not contain important performance information such as read/write block times, co-sim depth, and stall times.

You must apply the DATAFLOW pragma or directive to your design for the Dataflow Viewer report to be generated. You can apply dataflow to the top-level function, or specify regions of a function, or loops. The Dataflow viewer displays a representation of the dataflow graph structure, showing the different processes and the underlying producer-consumer connections. The Synthesis Summary, the Module Hierarchy, and the Function Call Graph will display the icon beside the top-level function to indicate the presence of the DATAFLOW pragma.

Tip: The diagram below is generated from the default m_axi interface of the Vitis Kernel flow as described in Target Flow Overview. The use of the Vivado IP flow can result in a different dataflow diagram.
Figure 1. Dataflow Viewer

Features of the Dataflow viewer include the following:

  • Source Code browser
  • Automatic cross-probing from process/channel to source code.
  • Filtering of ports and channel types.
  • Process and Channel table details the characteristics of the design:
    • Channel Profiling (FIFO sizes etc), enabled from the C/RTL Cosimulation settings in the Config File Editor.
      Important: You must use cosim.enable_dataflow_profiling=true in the HLS config file to capture data for the Dataflow viewer, and your test bench must run at least two iterations of the top-level function.
    • Process Read Blocking/Write Blocking/Stalling Time reported after RTL co-simulation.
    • Process Latency and II displayed.
    • Channel type and widths are displayed in the Channel table.
    • Automatic cross-probing from Process and Channel table to the Graph and Source browser.
    • Hover over channel or process to display tooltips with design information.

The Dataflow viewer can help with performance debugging your designs. When your design deadlocks during RTL co-simulation, the GUI will open the Dataflow viewer and highlight the channels and processes involved in the deadlock so you can determine if the cause is insufficient FIFO depth, for instance.

When your design does not perform as expected, the Process and Channels table can help you understand why. A process can stall waiting to read input, or can stall because it cannot write output. The channel table provides you with stalling percentages, as well as identifying if the process is "read blocked" or "write blocked."

The Dataflow Viewer displays a menu bar at the top of the report that includes the following features:

  • Zoom In/Zoom Out/Zoom Fit commands
  • Toggle Table command to show or hide the table beneath the graph
  • Group All/Ungroup All groups associated channels together to simpligy the diagram
  • Legend command for the display.