By default, Vitis HLS implements the AXI4 port with a 64-bit address bus.
However, some devices such as the Zynq 7000 have a 32
bit address bus. In this case you can implement the AXI4 interface with a 32-bit address
bus by setting the
syn.interface.m_axi_addr64=0
configuration command to disable the 64-bit address bus.Important: When you
disable the
syn.interface.m_axi_addr64 option, the
HLS tool implements all AXI4 interfaces in the design with a 32-bit address
bus.