Cosim Deadlock Detection - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

A deadlock is a situation in which processes inside a DATAFLOW region share the same channels, effectively preventing each other from writing to it or reading from it, resulting in both processes getting stuck. This scenario is common when there are either FIFO’s or a mix of PIPOs and FIFOs as channels inside the DATAFLOW. Deadlock detection visualizes this scenario on the Dataflow Viewer report, as shown in the following figure.

Figure 1. Deadlock Viewer

Deadlock detection, which is enabled by default, highlights any problematic processes and channels in the Dataflow Viewer when they are encountered during C/RTL Co-simulation. The Dataflow report opens automatically opens after co-simulation detects the deadlock situation. The viewer also provides a cross-probing capability to link between the problematic dataflow channels and the associated source code. You can use the information in solving the issue with less time and effort. You can disable the feature using the cosim.disable_deadlock_detection config file command.

In the example shown above the dataflow region consists of two processes which are communicating through PIPO and FIFO. The first loop in proc_1 writes 10 data items in data_channel1, before writing anything in data_array. Because of the insufficient FIFO depth the data_channel loop does not complete which blocks the rest of the process. Then proc_2 stalls because it cannot read the data from data_channel2 (because it is empty), and cannot remove data from data_channel1. This creates a deadlock that requires increasing the size of data_channel1 to at least 10. This example is demonstrated in the deadlock detection portion of the 03-dataflow_debug_and_optimization tutorial on GitHub.

The output of the C/RTL Co-Simulation process is shown below. The simulation ends in an error because of the deadlock detection, and the Dataflow Viewer report is opened automatically.

// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
// RTL Simulation : 0 / 1 [0.00%] @ "105000"
// Dependence cycle 1:
// (1): Process: example_example.proc_1_U0
//      Channel: example_example.data_channel1_U, FULL
// (2): Process: example_example.proc_2_U0
//      Channel: example_example.data_array_U, EMPTY
// Totally 1 cycles detected!