Co-Simulation Configuration - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2023-12-18
Version
2023.2 English

The cosim options apply to the C/RTL Co-Simulation process used to validate the RTL produced by HLS synthesis. This includes using the C/C++ test bench used earlier in C-simulation and using the RTL design in behavioral simulation as described in C/RTL Co-Simulation in Vitis HLS in the Vitis HLS User Guide (UG1399).

cosim.O
Enables optimizing compilation which eliminates debug constructs. The default is false and compilation is done in debug mode to enable debugging. Enabling optimized compilation of the C/C++ test bench and RTL wrapper increases compilation time, but results in better run time performance.
cosim.O=true
cosim.argv
Specifies an argument list for the behavioral test bench. The specified <arg> will be passed to the main() function in the C test bench.
cosim.argv=arg1 arg2
cosim.compiled_library_dir
Specifies the compiled library directory used during simulation with third-party simulators. The <arg> is the path name to the compiled library directory. The library must be compiled ahead of time using the compile_simlib command as explained in the Vivado Design Suite Tcl Command Reference Guide (UG835).
cosim.compiled_library_dir=../../simLib
cosim.coverage
Enables the coverage feature during simulation with the VCS simulator.
cosim.coverage=true
cosim.disable_binary_tv
Disables the binary test vector format in co-simulation.
cosim.disable_binary_tv=true
cosim.disable_deadlock_detection
Disables deadlock detection, and opening the Cosim Deadlock Viewer in co-simulation.
cosim.disable_deadlock_detection=true
cosim.disable_dependency_check
Disables dependency checks when running co-simulation.
cosim.disable_dependency_check=true
cosim.enable_dataflow_profiling
This option enables the dataflow channel profiling to track channel sizes during co-simulation. You must enable this feature to capture dataflow data as described in the Dataflow viewer section of the Vitis HLS User Guide (UG1399).
cosim.enable_dataflow_profiling=true
cosim.enable_fifo_sizing
Enables automatic FIFO channel size tuning for dataflow profiling during co-simulation.
cosim.enable_fifo_sizing=true
cosim.enable_tasks_with_m_axi
Enables stable m_axi interfaces for use with hls::task.
cosim.enable_tasks_with_m_axi=true
cosim.hwemu_trace_dir
Specifies the location of test vectors generated during hardware emulation to be used as a test bench during co-simulation. The test vectors are generated by the syn.rtl.cosim_trace_generation command as described in RTL Configuration. This argument lets you specify the kernel and instance name of the Vitis kernel in the hardware emulation simulation results to locate the test vectors for the HLS component.
cosim.hwemu_trace_dir=../../dct/dct_2
cosim.ldflags <arg>
Specifies the options passed to the linker for simulation. This option is typically used to pass include path information or library information for the C/C++ test bench.
cosim.ldflags=ldExample
cosim.mflags <arg>
Provides for options to be passed to the compiler for C simulation. This is typically used to speed up compilation.
cosim.mflags=mExample
cosim.random_stall
Enable random stalling of top level interfaces during co-simulation.
cosim.random_stall=true
cosim.rtl
Specifies either Verilog or VHDL as the language to use for C/RTL co-simulation. The default is Verilog.
cosim.rtl=vhdl
cosim.setup
When this option is specified, the simulation binary will be created in the cosim directory of the current HLS component, but simulation will not be executed. Simulation can be launched later from the compiled executable. The default is false, and co-simulation is run after setup is complete.
cosim.setup=true
cosim.stable_axilite_update
Enable s_axilite to configure registers which are stable compared with the prior transaction.
cosim.stable_axilite_update=true
cosim.tool

Specify the HDL simulator to be used to co-simulate the RTL with the C testbench. The Vivado simulator (xsim) is the default, unless otherwise specified.

  • auto
  • vcs
  • modelsim
  • riviera
  • isim
  • xsim
  • ncsim
  • xceilum
cosim.tool=modelsim
cosim.trace_level

Determines the level of waveform trace data to save during C/RTL co-simulation.

  • none does not save trace data. This is the default.
  • all results in all port and signal waveforms being saved to the trace file.
  • port only saves waveform traces for the top-level ports.
  • port_hier save the trace information for all ports in the design hierarchy.
cosim.trace_level=port

The trace file is saved in the sim/Verilog or sim/VHDL folder of the component when the simulation executes, depending on the selection used with the cosim.rtl option.

cosim.user_stall
Specifies the JSON stall file to be used during co-simulation. The stall file can be generated using the cosim_stall command.
cosim.user_stall=../../stall.json
cosim.wave_debug
Opens the Vivado simulator GUI to view waveforms and simulation results. Enables waveform viewing of all processes in the generated RTL, as in the dataflow and sequential processes. This option is only supported when using Vitis simulator for co-simulation by setting cosim.tool=xsim. See Viewing Simulation Waveforms for more information.
cosim.wave_debug=true