Arrays on the Interface - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English

When you use an array as an argument to the top-level function, Vitis HLS assumes one of the following:

  • Memory is off-chip and Vitis HLS synthesizes M_AXI ports on the interface to access the memory as the default for the Vitis Kernel flow.
  • Memory is standard block RAM with a latency of 1 as the default behavior in the Vivado IP flow. The data is ready one clock cycle after the address is supplied.

To configure how Vitis HLS creates these ports:

  • Specify the interface as a M_AXI, BRAM, or FIFO interface using the INTERFACE pragma or directive.
  • Specify the RAM as a single or dual-port RAM using the storage_type option of the INTERFACE pragma or directive.
  • Specify the RAM latency using the latency option of the INTERFACE pragma or directive.
  • Use array optimization directives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigure the structure of the array and therefore, the number of I/O ports.
Tip: Because access to the data is limited through a memory (RAM or FIFO) port, arrays on the interface can create a performance bottleneck. Typically, you can overcome these bottlenecks using optimization directives.
Arrays must be sized when used in synthesizable code. If, for example, the declaration d_i[4] in Array Interfaces is changed to d_i[], Vitis HLS issues a message that the design cannot be synthesized:
@E [SYNCHK-61] array_RAM.c:52: unsupported memory access on variable 'd_i' which is (or contains) an array with unknown size at compile time.