AXI Adapter Interface Protocols - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English
Important: As discussed in Interfaces for Vitis Kernel Flow, the AXI4 adapter interfaces are the default interfaces used by Vitis HLS for the Vitis Application Acceleration Development flow, though they are also supported in the Vivado IP flow. The AXI4-Stream Accelerator Adapter is a soft AMD LogiCOREā„¢ Intellectual Property (IP) core used as a infrastructure block for connecting hardware accelerators to embedded CPUs.

The AXI4 interfaces supported by Vitis HLS include the AXI4-Stream interface (axis), AXI4-Lite (s_axilite), and AXI4 master (m_axi) interfaces. For a complete description of the AXI4 interfaces, including timing and ports, see the Vivado Design Suite: AXI Reference Guide (UG1037). As described in the following sections, the AXI4 interfaces implement an adapter to manage communication according to the protocol. None of the other available Vitis HLS interfaces implement such an adapter.

Specify on arrays and pointers (and references in C++) only. The m_axi mode specifies an AXI4 Memory Mapped interface.
Tip: You can group bundle arguments into a single m_axi interface.
Specify this protocol on any type of argument except streams. The s_axilite mode specifies an AXI4-Lite slave interface.
Tip: You can bundle multiple arguments into a single s_axilite interface.
Specify this protocol on input arguments or output arguments only, not on input/output arguments. The axis mode specifies an AXI4-Stream interface.
Tip: The AXI protocol requires an active-Low reset. If your design uses AXI interfaces the tool will define this reset level with a warning if the syn.rtl.reset_level is active-High, which is the default setting.