In the common comand-line flow the Vitis
compiler supports a single approach to clock management using the v++ --freqhz option. It is supported for AI Engine graph compilation,
HLS component synthesis, and System project linking.
The process for managing clock frequencies in AI Engine components, HLS components, or System projects includes the following:
- Default values
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-
--part: The device doesn't contain a default clock, so the default depends upon whether you are targeting HLS, AI Engine, or system linking as described below. -
--platform: A platform specifies a default clock, which is passed to thev++option. You can override the default platform clock by using the--freqhzoption.
-
- v++ -c --mode aie
-
-
--part: The default clock is ¼ of the AI Engine PLL frequency. -
--platform: The default clock is derived from the platform, and can be overridden using the--freqhzoption.
-
- v++ -c --mode hls
-
-
--part: The default clock is derived from--hls.clock=10ns. -
--platform: The default clock is derived from the platform, and can be overridden using the--freqhzoption. Specifying a different--hls.clockfrequency will result in an error during thev++ --mode hlsoption.
-
- v++ -c -k
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-
--part: This is unsupported for v++ -c -k. The default clock is defined by the platform. -
--platform: The default clock is derived from the platform, and can be overridden using the--freqhzoption.
-
- v++ --link
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--part: For Versal devices, the--partoption specifies a default value of 300 MHz. For other devices,--partis unsupported. A default clock is defined by the platform. -
--platform: The default clock is derived from the platform, and can be overridden using the--freqhzoption.
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