Syncing Clocks with the AI Engine - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

PLIO represents an ADF graph interface to a PL component. This component could be a PL kernel, a platform IP representing a signal source or sink, or it could be a data mover to interface the ADF graph to memory. You should provide clock frequency values for these interfaces to ensure simulation results match the results from running the design in hardware.  In addition, when you link the ADF graph into the platform using the v++ -link command, you can direct the tools to generate precisely the clock frequencies required by your application. PL kernels can be independently clocked, and the v++ linker will automatically insert clock domain crossing circuitry into the design as needed.

The recommended best practice is to use the --freqhz option to specify all clocks as follows:

  1. When all PLIOs will be clocked at the same frequency, use v++ -c --mode aie --freqhz to specify. When different PLIOs will run at different clock frequencies, specify frequencies in the ADF graph PLIO constructors. If the PLIO clock frequencies are not known at AI Engine compilation time, they can be specified at v++ link time.
    v++ -c --mode aie --freqhz <frequency>
  2. Provide the same frequency to the Vitis compilation of the attached PL kernel:
    v++ -c --mode hls -freqhz <frequency>
  3. Provide the same frequency to the Vitis linker (v++ -l) when linking the AI Engine graph to the PL kernels and the platform in the System project. At v++ link time, individual kernel clocks can also be specified with the --clock.freqhz directive.
    v++ -l --platform <pfm_name> --freqhz <frequency>