Special Considerations for Embedded Platform Creation - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
Release Date
2023.2 English

Divide Logic Functions to Platform and Kernel

While the designs on FPGA and SoC are getting more complex, it is common for multiple developers or teams to work on a design together. The Vitis software platform provides a clear boundary for application developers and platform developers. Platform developers could include board developers, BSP developers, system software developers, and so on.

In the view of a system architect, some logic functions might be in a gray area: they can be packaged with platforms, or they can work as an acceleration kernel. To help divide the system blocks, here are some general guidelines.

  • When a component can be classified as either platform or acceleration kernel, set it as a kernel. The platform should be designed as thin as possible to help reduce the platform repackaging effort when this component needs an update. Also, if you iterate during the development phase, it can save time.
  • Platforms should be the abstraction of hardware. When changing a hardware board, the application does not require changes, or very few changes if necessary, to target the new hardware.
  • IPs in the platform are controlled by device tree and Linux drivers, acceleration kernels are controlled by XRT. If some IP needs standard Linux driver support, package them into the platform and describe them in the device tree.
  • Acceleration kernels usually have standalone features and simple datapath and control path connections. If some components provide infrastructural features shared by multiple kernels or they have complicated connections with other modules, they usually can be packaged in the platform.

The following table shows the recommended platforms and kernels for logic types.

Table 1. Recommended Platforms and Kernels
Logic Platform Kernel
Hard Processors (PS of 7000 SoC and Zynq UltraScale+ MPSoC) Only in Platform  
Soft Processors Preferred in Platform OK as an RTL kernel
I/O Interface IP with GPIO and SerDes (External pins, MIPI, Aurora, etc.) Only in Platform  
I/O Interface Companion IP (DMA for PCIe® , Ethernet MAC for Ethernet PHY, etc.) Standard and stable IP should be placed in the platform if they are not application specific. Customized companion IP can work as acceleration kernels.
Traditional memory mapped IP which needs standard Linux driver (VPSS, etc.) Only in Platform  
HLS AXI memory mapped IP OK in Platform. Need to write control software or driver manually. Preferred as Kernel. Controlled by XRT.
Acceleration memory mapped IP follows Vitis kernel register standard and open to XRT   Preferred as Kernel
Vitis Libraries   Only work as Kernel


For more information on embedded platforms, see the following links: