The following steps are required to run
the Xilinx virtual cable (XVC) and HW servers, host applications, and also trigger and
arm the debug cores in the Vivado hardware
manager.
- Add debug IP to the kernel as discussed in Enabling Kernels for Debugging with Chipscope.
- Modify the host program to pause at the appropriate point as described in Enabling ILA Triggers for Hardware Debug.
- Set up the environment for hardware debug, using an automated script described in Automated Setup for Hardware Debug, or manually as described in Manual Setup for Hardware Debug.
- Run the hardware debug flow using the following process:
- Launch the required XVC and the
hw_server
of the Vivado hardware manager. - Run the host program and pause at the appropriate point to enable setup of the ILA triggers.
- Open the Vivado hardware manager and connect to the XVC server.
- Set up ILA trigger conditions for the design.
- Continue execution of the host program.
- Inspect kernel activity in the Vivado hardware manager.
- Rerun iteratively from step b (above) as required.
- Launch the required XVC and the