Kernel Interface Requirements - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

To enable the Vitis compiler to connect kernels into the target platform, an RTL kernel must adhere to the requirements described in PL Kernel Properties. The various interface requirements are summarized in the following table.

Important: In some cases, the port names must be defined exactly as shown.
Table 1. RTL Kernel Interface and Port Requirements
Port or Interface Description Comment
Clock One or more clock inputs.
  • At least one clock is required for the kernel. 1
  • Can be named anything, but must be packaged with a bus interface.
    Important: All ports in the RTL IP must be associated with an interface when packaging the RTL for use in the Vitis environment. If this is not the case, an error similar to the following occurs:
    ERROR: UNDEF When packaging for Vitis, pins that are not part of an interface are not supported
Reset Primary active-Low reset input port
  • Optional port.
  • Can be named anything, but must be associated with a Clock signal through the ASSOCIATED_RESET property on the Clock.
  • This signal should be internally pipelined to improve timing.
  • The signal is driven by a synchronous reset in the associated Clock domain.
interrupt Active-High interrupt.
  • Optional port.
  • When used, the name must be exactly as shown.
s_axi_control One (and only one) AXI4-Lite slave control interface
  • Required port. The s_axilite interface is generally required with exception for some cases using AXI4-Stream interfaces. It is not required for non-software controlled kernels.
  • When used, the name must be exactly as shown, and is case-sensitive.
Tip: The address range of the s_axilite interface can be edited in the kernel.xml file and repackaged using the package_xo command if needed. However, XRT imposes a 64K (16 bit) address range limitation. The tool will return an error if the s_axilite interface is greater than 16 bits wide.
AXI4_Memory Mapped Interface (m_axi) AXI4 memory mapped interfaces for global memory access
  • Optional port.
  • All AXI4 memory mapped interfaces must have 64-bit addresses (32 bits on AMD Zynq™ 7000 devices).
  • The RTL kernel developer is responsible for partitioning global memory spaces. Each partition in the global memory becomes a kernel argument. The memory offset for each partition must be provided by the SW applications to the kernel through a register in the AXI4-Lite interface.
  • AXI4 memory mapped must not use Wrap or Fixed burst types and must not use narrow (sub-size) bursts. This means that AxSIZE should match the width of the AXI data bus.
  • Any user logic or RTL code that does not conform to the requirements above, must be wrapped or bridged to satisfy these requirements.
AXI4_STREAM (axis) AXI4-Stream interfaces for one-way data transfers between kernels or between the host application and kernels.
  • Optional port.
  • Cannot be used with bi-directional ports.
  • Use the STREAM interface template in the Vivado Design Suite.
  • Refer to AXI4-Stream Interfaces in the Vitis HLS User Guide (UG1399) for additional information on interface requirements.
  1. The clock requirements listed here are for newer platform shells which include fixed clocks as discussed in Managing Clock Frequencies. RTL kernels for use on legacy platforms support two clocks named ap_clk and ap_clk_2 specifically, and two optional resets named ap_rst_n and ap_rst_n_2.