Generating sim_ipc_axis IP for Vivado Project - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

By default, the python script generates aie_wrapper_ext_tb_ip.tcl and aie_wrapper_ext_tb_proj.tcl along with the wrapper Verilog file as mentioned in the previous section.

There are two ways to proceed based on the existence of a Vivado project:

  1. If you have already created Vivado project, use the IP flow described here. From the Tcl console source the aie_wrapper_ext_tb_ip.tcl script:

    source <absolute_path>/aie_wrapper_ext_tb_ip.tcl

    This Tcl script can be used for generating required sim_ipc_axis IP. After sourcing the Tcl file you will see hierarchy created under simulation_sources. You can add the required files and directories for your project .

  2. If a Vivado project is not already created, use the project script aie_wrapper_ext_tb_proj.tcl to create one. From a terminal use the following command:

    vivado -mode batch -source aie_wrapper_ext_tb_proj.tcl 
    Note: To use third party simulators, you need to update the required paths for SIMULATOR_GCC_PATH, SIMULATOR_CLIBS_PATH and INSTALL_BIN_PATH. For more details on how to set the third party simulators, refer to the Logic Simulation chapter of Vivado Design Suite User Guide: Logic Simulation (UG900)

    After sourcing aie_wrapper_ext_tb_proj.tcl, the tool will generate the export_sim directory with sub-directories and scripts required for use with other simulators. This Tcl script sources the aie_wrapper_ext_tb_ip.tcl script.

Tip: The scripts mentioned above only contain the sim_ipc_axis modules, so you must add any additional required RTL modules and options to the script. You can modify and directly include required RTL the needed script.