Generating and Opening the Timeline Trace - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
Release Date
2023.2 English

To generate the Timeline Trace report, you must complete the following steps to enable timeline and device trace data collection in the command line flow:

  1. Instrument the FPGA binary during linking, by adding Acceleration Monitors and AXI Performance Monitors to kernels using the v++ --profile option as described in --profile Options. As an example, add to the v++ linking command line:
    v++ -g -l all:all:all ...
  2. After the kernels are instrumented during the build process, data gathering must also be enabled during the runtime execution of the application by editing the xrt.ini file. Refer to xrt.ini File for more information.

    The following xrt.ini file enables maximum information gathering when the application is run:

    Tip: If you are collecting a large amount of trace data, you might need to use the --profile.trace_memory with the v++ command, and the trace_buffer_size keyword in the xrt.ini.

    After running the application, the Timeline Trace data is captured in CSV files called opencl_trace.csv and device_trace_0.csv.

  3. The CSV report can be viewed in the Vitis analyzer tool by opening the Run Summary produced during the application execution. You can launch the Vitis analyzer and open the Run Summary using the following command:
    vitis_analyzer xrt.run_summary
    Tip: By default, the Timeline Trace is displayed in a hierarchical view, which presents the information according to design hierarchy but consumes significant real estate in the display. As an alternative, you can "flatten" the timeline display to eliminate unnecessary spacing between lines. Perform this by selecting the Flatten Signal command on the toolbar. This feature is useful when there is less display area to work with, or when comparing multiple trace files.