External RTL Traffic Generator and Emulation Process - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

External RTL traffic generators are used to drive traffic to Vitis emulation process or AI Engine simulation process using SystemVerilog or Verilog modules.

Figure 1. Test Bench Hierarchy

As shown in the figure above, the external test bench (on the left) and the Vitis emulation (on the right), both run as separate simulation processes. To establish communication between two processes using IPC, you must instantiate SIM_IPC Master/Slave modules.

Perform the following modifications:

  1. You need to create a project in Vivado simulator. For details on how to create a project, refer Vivado Design Suite User Guide: Design Flows Overview (UG892)
  2. Once the project is created, you need to instantiate sim_ipc IP in the external SV/Verilog testbench.
  3. Then run the export_simulation command in Vivado to generate the scripts for the simulation
  4. Run the simulation in Vivado simulator. For details running simulation refer to Vivado Design Suite User Guide: Logic Simulation (UG900)