External RTL Traffic Generator and AI Engine Simulation - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

The same technique can be deployed to drive traffic from the external System Verilog/Verilog traffic generators/test benches to the AI Engine simulator or x86-simulator.

Figure 1. XTLM Test Bench Hierarchy

To generate the AI Engine wrapper stub module (aie_wrapper_ext_tb.v) use the following steps:

  1. The wrapper stubs will be generated based on the external PLIO declarations in the ADF graph. You need to perform the ADF graph compilation to generate scsim_config.json file that resides in ./Work/config/scsim_config.json directory. This config file contains information on the PLIOs declared in the graph. For more details on how to perform ADF graph compilation and external PLIOs declaration, refer to AI Engine Tools and Flows User Guide (UG1076).
  2. You can use this config file as argument to the gen_aie_wrapper.py script to auto-generate Verilog stub modules based on ext PLIO declared in ADF Graph:
    python3 ${XILINX_VITIS}/data/emulation/scripts/gen_aie_wrapper.py \
    -json Work/config/scsim_config.json --mode <wrapper/vivado> 
    Tip: The python script is available in the Vitis installation area as shown in the example above. There are two modes for the script: wrapper and Vivado mode. By default, the script runs in Vivado mode.

The name of the instance stubs must be identical to the name of the corresponding external PLIOs in the graph and will be reflected in the generated aie_wrapper_ext_tb.v file.

After running the gen_aie_wrapper.py script, theaie_wrapper_ext_tb.v is generated with instances of sim_ipc_axis modules that can be directly instantiated in your external test bench.

Note: The module used to send data to/from external traffic generator to AI Engine simulator/x86sim are the XTLM IPC SystemC modules which are present inside the wrapper stub module which includes all the XTLM IPC modules. This wrapper needs to be instantiated in the external test bench to establish the connection as shown in the figure above.