Enabling Profile and Debug when Linking - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

To capture and visualize profiling and trace information, or to enable your design for debugging, you will need to add specific commands during the v++ linking phase, and sometimes during v++ compilation. The tool must instrument the profile IP using --profile Options in the v++ linking phase and enable the profiling during the runtime. To enable debugging the application you can specify on of the --debug Options.

During v++ linking, the application developer needs to add profile IP to the design to capture the profiling data and preferably choose the memory resources for storing and offloading data during the runtime.

  • You can add PL monitors to capture tracing information on their design by using --profile command. This adds the logic to capture profile data for data traffic between the kernel and host, kernel stalls, the execution times of kernels, and compute units (CUs). The instrumentation can be added using options, --profile.data, --profile.stall, and --profile.exec, as described in the --profile Options.
  • You also can specify the choice of memory resources or FIFO in the PL to store captured data. On large designs that span multiple SLRs, the tracing infrastructure can cause timing issues as there is one offload point and all trace data must cross SLRs to reach it. For these use cases, multiple memory resources can be used for offloading the trace data.

To enable the capture of profile data or trace information during the application runtime, you can choose from a variety of options to add to the xrt.ini File which configures the runtime. See Profiling the Application for more information.