Debug and Verification Considerations - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English
  • RTL kernels should be verified in their own test bench using advanced verification techniques including verification components, randomization, and protocol checkers. The AXI Verification IP (VIP) is available in the Vivado IP catalog and can help with the verification of AXI interfaces. The RTL kernel example designs contain an AXI VIP-based test bench with sample stimulus files.
  • You can add ILA inside of RTL kernels as described in Adding Debug IP to RTL Kernels.
  • Hardware emulation should be used to test the host code software integration or to view the interaction between multiple kernels.