Creating an HLS Component - 2023.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

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2023.2 English

In an HLS component, the tool synthesizes a C or C++ function into RTL code for implementation in the programmable logic (PL) region of an AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC, or AMD FPGA device. HLS components can be built, simulated, analyzed, and debugged as a standalone component in a bottom-up design flow. The creation of an HLS component is described in the Vitis HLS User Guide (UG1399). Refer to that document for more information on building and analyzing an HLS component.

The HLS component can be added to a System project as part of an embedded system design, or for application acceleration in a data center. The use of an HLS component in a larger system design is described in this document under Building and Running the System, or in the Vitis unified IDE as described under Creating a System Project for Heterogeneous Computing. Refer to that content for more information on using HLS components in a system design.