Validation - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

The different compute domains of AMD Versalâ„¢ device challenge traditional FPGA validation methods. In addition to programmable logic and a processor subsystem, Versal devices include AI Engines, making system validation a complex task compared to traditional FPGAs.

This validation methodology is built around the follow key concepts:

Block/IP Validation
The individual RTL and HLS IP in the PL can be validated individually before the system is integrated.
AI Engine Validation
AI Engines at the interface level can be viewed as AXI4 memory map or AXI4-Stream IP.
System Validation
After the individual blocks are validated, the entire system can be validated, using processors to coordinate data flow, test vector generation, monitor, etc.