The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 11/15/2023 Version 2023.2 | |
| Using SLR Crossing Registers | Updated example. |
| Using IMUX Registers to Improve Timing to Hard Macros | Added new section. |
| DRC Closure | Added new section |
| Improving NoC Performance | Revised section. |
| Debugging Configuration | Added new section. |
| Debugging Board Bring Up | Added new section. |
| Debugging Power | Added new section. |
| Debugging the NoC | Added link to NoC debug blog. |
| Debugging the DDR Memory Controllers | Added new section. |
| Debugging PCIe | Added new section. |
| 05/24/2023 Version 2023.1 | |
| Document title | Changed title to Versal Adaptive SoC System Integration and Validation Design Methodology Guide (UG1388). |
| Debugging the System | Added new section. |