Retaining Names of Debug Probe Nets Using MARK_DEBUG - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

You can mark a signal for debug either at the RTL stage or post-synthesis. The presence of the MARK_DEBUG attribute on the nets ensures that the nets are not replicated, retimed, removed, or otherwise optimized. You can apply the MARK_DEBUG attribute on top level ports, nets, hierarchical module ports and nets internal to hierarchical modules. This method is most likely to preserve HDL signal names post synthesis. Nets marked for debugging are shown in the Unassigned Debug Nets folder in the Debug window post synthesis.

Add the mark_debug attribute to HDL files as follows:


attribute mark_debug : string;
attribute mark_debug of sine   : signal is "true";


(* mark_debug = "true" *) wire sine;

You can also add nets for debugging in the post-synthesis netlist. These methods do not require HDL source modification. However, there might be situations where synthesis has not preserved the original RTL signals due to netlist optimization involving absorption or merging of design structures. Post-synthesis, you can add nets for debugging in any of the following ways:

  • Select a net in any of the design views (such as the Netlist or Schematic window), then right-click and select Mark Debug.
  • Select a net in any of the design views, then drag and drop the net into the Unassigned Debug Nets folder.
  • Use the net selector in the Set Up Debug wizard.
  • Set the MARK_DEBUG property using the Properties window or the Tcl Console.
    set_property mark_debug true [get_nets -hier [list {sine[*]}]]

    This applies the mark_debug property on the current, open netlist. This method is flexible, because you can turn MARK_DEBUG on and off through the Tcl command.