Limitations - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
Release Date
2023.2 English

Following are limitations when analyzing performance for the CPM or the PL PCIe:

  • Performance debug in simulation might not reflect the whole system behavior. Only simulating a CPM block can result in a fairly accurate performance model, however you must note the following simulation model limitations:
    • High power domain (HPD) and PS9 are modeled with a BFM. This BFM does not represent hardware in a cycle-accurate manner. This BFM also might require you to manually set parameters based on their IP settings, and might not propagate the same values used in hardware. The BFM might use a different clock frequency to speed-up simulation times through certain events. Or for simplicity, it might be modeled with a single clock domain that otherwise would not be in hardware.
    • When simulating CPM or PL PCIe as an Endpoint, AMD provides a Root Port PCIe model. It is not a BFM but it is based on PL PCIe IP architecture and most likely will have a more responsive turnaround time compared to a regular host system.
  • Hardware probing using ILA internal to the CPM or PS or NoC block is not possible, but NoC NMU and NSU can provide internal statistics such as packet counts. However, you must keep in mind that one bottleneck in the data pipeline will eventually spread throughout the entire data path. That is, if the slaves are throttling, the interconnects and masters can also look like they are throttling. Therefore this data might require more qualifications with other data before a final conclusion can be made.
  • Similar to the above point, in DMA operation, everything is done in a loop. If software or host is throttling, hardware will eventually throttle and vice versa.