Improving the Netlist with Block-Level Synthesis Strategies - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

Although most designs can meet timing requirements with the default Vivado synthesis settings, larger and more complex designs usually require a mix of synthesis strategies for different hierarchies to close timing.

For example, one module might benefit from the use of FF resources instead of SRLs to implement pipelining in the device, but the rest of the design might benefit from implementation of logic in SRLs rather than FFs to reduce spreading. In this case, set the ALTERNATE_ROUTABILITY strategy for the module that requires the use of FF resources, and synthesize the rest of the design using the Default strategy.

Note: For more information, see this link in the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).