Improving Performance in the PL - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

The following design characteristics define PL performance:

  • Maximum clock frequency achieved by the Vivado implementation tools
  • Latency through the various RTL blocks, either due to finite state machines (FSMs) or amount of pipelining
  • NoC efficiency given the achieved QoS and traffic pattern of the connected blocks
  • Power consumption given the thermal setup, design toggle rate, resource utilization, operating clock frequency, and target speed grade

To improve maximum PL clock frequency when meeting your power budget, do the following:

  • Use traditional analysis and closure techniques
  • Analyze the data movement inside the NoC
  • Validate that the measured bandwidth and traffic pattern in hardware matches the simulated results generated during design creation