ILA Core Designs with High-Speed Clocks - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

For designs with high-speed clocks, consider the following:

  • Limit the number and width of signals being debugged.
  • Pipeline the input probes to the AXIS-ILA by setting the number of input pipeline stages. This setting can be found in the Advanced tab of the AXIS-ILA GUI or set with the C_INPUT_PIPE_STAGES property when using Tcl insertion.