Generator and Checkers - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

You can use any of the following options for generators and checkers:

  • Off-the-shelf AXI-DMA or MCDMA IP from the Vivado IP integrator catalog, which can stream data from the DDR memory to the programmable logic. This method is the easiest way to bring the block to hardware. For more information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).
  • LFSR generator and checkers from the Vivado tools language templates. Alternatively, you can design your own version of a pseudo random data generator checker.
  • UltraRAM to block RAM, which can provide specific data to verify the functionality of the block.
    Note: You can embed RAM with initial memory contents (MEM files) and with additional circuitry (such as AXI GPIO), which gives you the flexibility to control the test harness.
  • AXI traffic generators (ATGs), which can generate pre-configured traffic types and can also be programmed to check for a desired length of data. Although this does not always provide a data integrity check, it is a quick way to validate the intent of the design under test.
  • AXI or AXI4-Stream ILA, which can monitor data at the output of design under test. Using this method, you can visually analyze the data using the Vivado IDE and visualize waveforms without much overhead. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).

After a test harness is built, you can test the design on hardware without any additional software. All the register interfaces are available through the Xilinx® System Debugger xsdb console in JTAG mode.

Alternatively, you can develop a software application to orchestrate generator and checker functions based on the register control interface. This method is particularly useful if the design process involves multiple IP and helpful if you want to reuse the validation infrastructure for different stages in design.