Debugging the DDR Memory Controller Interface - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2023-11-15
Version
2023.2 English

For help debugging the DDR memory controller interface, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). This product guide includes information on how to proceed after encountering an error at this link. This product guide also includes information on the individual steps to take and error messages that appear when a calibration error occurs at this link. When debugging a hardware-related issue, see this link in the Versal Adaptive SoC PCB Design User Guide (UG863) to ensure the memory interface meets the layout guidelines. When working on a DDR memory controller calibration error, use the smallest design possible for the hardware, which is typically a CIPS instance and the single NoC DDR memory controller that you are debugging. To move past a calibration error, try to reduce the memory interface frequency or enable 2T timing for DDR4 under the DDR Advanced tab.

For an up-to-date list of known issues for the NoC and the DDR memory controller, see Answer Record 75764. For information on dual-channel DDR memory controller topologies, see Answer Record 76830. If an operating system is trying to use a memory space as described in this answer record, the OS will encounter unexpected errors during boot or during operation. This answer record also includes links to important design resources like the Versal ACAP DDRMC - DDR4 and LPDDR4/x PCB Simulation Support Article and Versal ACAP DDRMC - DDR4, LPDDR4, and LPDDR4X External Reference Clock Design Guidance Article. These articles describe how to generate IBIS models for PCB-level simulations, explain the IP generated default constraints for the DDR memory controller configuration, and provide guidance on how to design the external reference clock circuit for the DDR memory controller.

Because the Versal device DDR memory controller has a different set of limitations for generating a valid pinout, you must make sure a pinout was generated by following the Obtaining and Verifying Versal ACAP Memory Pinouts Tutorial. If you encounter an issue at the Validate Design stage, see Answer Record 35164. If you plan to increase the memory density in the future while using a hardware design, see this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) when generating a pinout for the Versal device.

If there are post-calibration data errors with the DDR memory controller, use the Versal ACAP DDR Memory Controller - 2D Eye Scan Tutorial. This tool generates a plot of the 2D data valid window on a per nibble basis for the memory interface. If the data valid window is small or has an anomalous shape, this might indicate a PCB layout or power issue. For PCB layout or power issues, try operating the interface at a lower data rate to see if the rate of data errors decreases or goes away entirely. Enabling 2T timing can also help if this option was not already enabled in the original hardware design. You can run the 2D Eye Scan once to get a baseline, and then run the 2D Eye Scan again after enabling 2T timing and lowering the data rate to determine whether the data valid window size improves.