Debugging DDR Memory Controller Performance - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2023-11-15
Version
2023.2 English

Every connection through the NoC has an associated QoS requirement. For information on supported QoS settings and their impact for a particular traffic type, see this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). For guidance on NoC and DDR memory controller performance tuning, see the Versal Network on Chip/DDR Memory Controller Performance Tuning Tutorial available from the GitHub repository.

The Versal Network on Chip/DDR Memory Controller Performance Tuning Tutorial uses the Performance AXI Traffic Generators documented in the Performance AXI Traffic Generator Product Guide (PG381). These traffic generators are the fundamental building blocks for modeling mission mode traffic patterns in both simulation and in hardware. To ensure a successful Versal device based design, the system-level traffic patterns and requirements must be understood and then translated in to the QoS requirements during design entry with the Vivado IP integrator. After the desired QoS result is achieved, the next step is to model this in simulation with the Performance AXI Traffic Generators. The Versal Network on Chip Performance AXI Traffic Generator Tutorials demonstrate two performance traffic generator use cases. One is the Non-Synthesizable Traffic Generator, which is for simulations only. The other is the Synthesizable Traffic Generator, which can be used in both simulation and hardware.

When debugging performance issues, you must consider the traffic sources in the design and how the traffic sources access the memory. This includes the size, length, and alignment of the AXI commands and how these commands interact with the DDR memory controller. You must also understand the memory interface technology, the memory interface topology, the DDR memory controller address mapping, and whether channel interleaving is enabled. Many performance issues are caused by sub-optimal access patterns from the traffic sources, including how the traffic sources are accessing the DDR memory controller address mapping. The Versal device DDR memory controller has sophisticated reordering capabilities, but the design must also consider the underlying DDR memory controller protocol limitations. The Command Decode module for simulation is a useful tool for viewing and analyzing the DDR memory controller protocol execution for a given access pattern. The AMD Versal Adaptive SoC: Performance Analysis in Simulation Tutorial demonstrates how to use this tool for a DDR4 scenario.