Block and IP Validation - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

The PL for the system can include different types of IP. If the IP is compliant with the AMD Vitis™ environment (that is, the interfaces to the IP are only AXI4 memory mapped, AXI4-Stream, clocks, and reset), you can use an existing Vitis platform from the installation area to integrate the blocks with a generator and checker logic. If the IP has unique ports that are not compliant with the Vitis environment, you can develop wrappers around the IP to make them compliant or use traditional AMD Vivado™ IP integrator methods to integrate the design with generators and checkers.

The following figure shows a generalized block validation design.

Figure 1. Generalized Block Validation Design