Analyzing Master Transactions - 2023.2 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2023.2 English

If the master injection rate is not the cause of the bottleneck or the redesign effort was deemed too high, inspect the master behavior to confirm that it is efficient. This analysis requires the instantiation of an ILA in the interface monitor mode. The ILA must be connected to the master M_AXI (S/MM) port. For PS masters, this might require routing into the PL. For other types of masters, this is not possible, and this section does not apply. For information on ILA instantiation, IP configuration, and debug techniques see this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Set the trigger position to be the beginning of the window, and issue a trigger immediately with mission data flowing through the master towards the NoC. If the master stalls, this indicates that the master behavior is causing some of the degradation in performance. The next step is to debug the master performance directly.

If the master does not stall, review the AXI transactions in detail to confirm the AXI burst size, length (bit-width of the interface), and addressing modes. Usually larger burst lengths, wider bit-width, and linear increasing address modes lead to high bandwidth. Also, confirm in hardware that the AXI clock is running at the specified frequency.

If any design changes are required, a rebuild and retest is required to improve NoC performance. If no issues are identified within the AXI master behavior, switching characteristics in the NoC might be the cause of performance issues.