XPIO Global Clock Buffer Clock Enable Timing - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Even at lower clock frequencies, it might be difficult to meet the setup timing requirement on a global clock buffer enable pin. The setup timing path challenges is due to the combination of:

  • The late enable edge where the launch clock uses global clock routing followed by the route from flip-flop crossing the boundary logic interface (BLI) to reach the enable pin.
  • The early capture clock edge arriving directly at the gated global clock buffer input pin without routing through the global clock network.
Figure 1. Global Clock Buffer Clock Enable Circuit

You can use the following techniques to improve timing to the global clock buffer enable pins:

  • Use the HARDSYNC feature on the global clock buffers that use a three-stage internal synchronizer. This removes the timing requirement but incurs a three or four clock-cycle latency on the clock output.
  • Use a negative phase-shifted clock to drive the enable control logic and pull in the launch clock edge.
  • Use the CLOCK_LOW_FANOUT constraint on the clock used to drive the enable control logic. This reduces the clock insertion delay on the source clock path by keeping it local to the adjacent clock region. The clock net must have a limited number of loads for this constraint to properly work.
  • Use the BLI constraint on the flip-flop that directly drives the global clock buffer. The BUFGCE clock enable pins do not have an associated BLI flip-flop resource. Therefore, you must use a BUFGCE_DIV with a divide of 1 or a BUFGCTRL when using the BLI flip-flop.
  • Use a cascaded buffer to drive the gated clock buffer and ensure the following:
    • Cascaded buffer is not optimized away
    • Cascaded buffer is placed in the same CLOCK REGION as the gated clock buffer
    • Cascaded buffer and buffer driving the enable control logic are balanced
Note: When using the HARDSYNC clock buffer mode, you must ensure the phase relationship between the gated buffer clock and other design clocks is not affected, especially for clocks with integral period ratios, such as 2, 4, 8, etc. If the relationship can change, you must consider this clock as asynchronous to other clocks in the design by adding appropriate timing constraints and circuitry.