Vitis HLS Methodology - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

Vitis HLS supports the following flow targets:

Vivado IP Flow
Supports a variety of interfaces and data transfer protocols, provides multiple design choices, and is more flexible. However, you must handle the integration and management of the IP. For information on how to enable this flow in Vitis HLS, see this link in the Vitis High-Level Synthesis User Guide (UG1399).
Vitis Kernel Flow
Supports a specific set of interfaces and is more restrictive. This more structured flow allows correct-by-construction integration of HLS blocks with Vitis extensible platforms and enables seamless integration with the Xilinx Runtime (XRT) software stack, greatly simplifying the hardware/software integration process. For information on how to enable this flow in Vitis HLS, see this link in the Vitis High-Level Synthesis User Guide (UG1399).

When targeting AMD Versalâ„¢ devices, you must configure the Vitis HLS project based on the design flow (traditional design flow or platform-based design flow) and based on how the resulting block will be used in the overall project, as shown in the following table.

Table 1. Versal Devices Vitis HLS Project Types
Design Flow Vitis HLS Output Flow Target Targeted User
Traditional design flow Integrated with other RTL and IP blocks Vivado IP flow Hardware designer
Platform-based design flow Integrated in the extensible platform Vivado IP flow Hardware designer
Platform-based design flow Linked as a kernel to the extensible platform Vitis kernel flow Hardware designer or software developer