Versal Device Clocking - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Versal devices have a clocking structure similar to AMD UltraScale™ devices, where global clocking is used throughout the device but the loads can be placed regionally or globally. Multi-clock buffer (MBUFG) primitives in Versal devices allow for clock division at the leaf level to reduce clock track utilization and improve timing on synchronous clock domain crossings. This architecture results in an efficient clock resource utilization, support for an increased number of design clocks, and improved clock characteristics for performance and power.

In Versal devices, clocks are typically sourced from the columnar HDIO banks or the horizontal high performance XPIO banks. Each Versal device clock region contains a clock network routing that is divided into 24 vertical routing tracks, 12 horizontal routing tracks, 24 vertical distribution tracks, and 24 horizontal distribution tracks. The bottom clock region row is unique and contains 24 horizontal routing tracks (versus the 12 horizontal routing tracks in the other clock region rows).

Figure 1. Versal Device Clock Routing Architecture

Following are the main categories of clock types and associated clock structures grouped by their driver and use:

  • High Speed I/O Clocks

    These clocks are associated with the SelectIO™ XPHY Logic and are generated by the XPLL. These clocks are routed via dedicated, low-jitter resources from the XPLL to the XPHY logic for high performance I/O interfaces. In general, this clocking structure is controlled by AMD IP, such as the NoC IP DDR4 memory controller, soft memory controller IP, or the Advanced IO Wizard IP.

  • General Clocks

    These clocks are used in most clock tree structures and can be sourced by a GCIO package pin or clock modifying blocks, such as an MMCM, XPLL, or DPLL. The general clocking network must be driven by the typical BUFGCE/BUFGCE_DIV/BUFGCTRL buffers or by the new MBUFGCE/MBUFGCE_DIV/MBUFGCTRL primitives that allow for leaf-level clock division. In HDIO banks, clocking is limited in terms of resources by only providing the DPLL and the BUFGCE. Any given clock region can support up to 24 unique clocks, and Versal devices can support over 100 clock trees depending on topology, fanout, and load placement.

  • Gigabit Transceiver Clocks

    The transmit, receive, and reference clocks of gigabit transceivers (GT*_QUAD) use dedicated clocking in the clock regions that include the GTs. In Versal devices, the GT clocking columns contain DPLLs and also support the new MBUFG_GT primitive for leaf-level clock division. You can use GT clocks to achieve the following:

    • Drive the DPLLs for frequency synthesis, jitter filtering, or clock deskew
    • Drive the general clocking network using the BUFG_GT or MBUFG_GT buffers to connect any loads in the fabric
    • Share clocks across several transceivers in the same or different Quad
    Note: Only the 12 even clock routing and clock distribution tracks cross the SLR boundary in the GT column.
    Note: No clock routing and clock distribution tracks cross the SLR boundary in the GT column to and from the top SLR of the AMD Versal™ HBM devices. Placer ignores a USER_CLOCK_ROOT in the GT column when loads are distributed between the top SLR and other SLRs.