Using the IMUX Register Constraint - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Optional flip-flop stages exist in the IRI_QUAD sites that drive Hard Macros in the PL. These IMUX registers (IMR) are organized into four IRI_QUAD sites per interface tile and are driven by the input routing MUXes.

For more information on using IMUX registers to improve timing to Hard Macros, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).

The IMRs can optimize the interface timing by registering signals driving into a hard block such as a block RAM, DSP, GT_QUAD, etc.

The following figure on the left shows the IRI_QUAD sites (highlighted in cyan) that drive a set of RAMB18 and RAMB36 sites (marked red). On the right side, a zoomed in view of one IRI_QUAD with the IMUX registers are (highlighted in cyan).

Figure 1. IMR in IRI_QUAD Example

IMR flip-flop resources have the following restrictions:

  • IMR only supports flip-flops with asynchronous clear (FDCE) or a synchronous reset (FDRE).
  • IMR only supports FDCE and FDRE with INIT value of 0.
  • All IMR flip-flops in a site must share the same active CLR signal or inactive GND R signal.
  • FDCE and FDRE can be mixed in a site only if the CLR pin and R-pins are tied to GND.
  • All IMR flip-flops in a IRI_QUAD site must share the same CE signal.
  • Only Data IMR Bels can be used. Control IMR Bels are not supported in Versal devices.

By default, flip-flops are not placed in IMR flip-flop resources if the flip-flops are simply connected to a hard block. The IMR constraint must be used for the Vivado tools to place flip-flops in the IMR flip-flop resources. If the IMR constraint cannot be met due to violation of the restrictions, the flip-flop is placed in the CLB. Nets of CLB flip-flops interfacing with resources using the IMR perform a route-through of the IMR flip-flop resources. In the following example, the IMR constraint is used for flip-flops in an IRI_QUAD driving BLI registers that drive MBUFGCE_DIV/CE. BLI (highlighted in magenta) and IMR (highlighted in cyan) sites are selected to obtain the optimal setup/hold window for the registers driving the MBUFGCE_DIVE/CE pins.

set_property IMR TRUE [get_cells {control_SLR1_ce_reg control_SLR2_ce_reg}]
Figure 2. IMR Constraint Example