Using LOC Constraints for IO/MMCM/XPLL/DPLL/GT - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

To constrain clocks, you can assign placement constraints as follows:

  • On a clock input at the I/O port

    Assigning a PACKAGE_PIN constraint for a clock on a GCIO or assigning a LOC to an IOB affects the clock network. The MMCM/XPLL/DPLL and clock buffers directly connected to the input port must be placed in the same clock region.


    The clock buffers directly connected to the MMCM/XPLL/DPLL outputs and the input clock ports connected to the MMCM/XPLL/DPLL inputs are automatically placed in the same clock region. If an input clock port and an MMCM/XPLL/DPLL are directly connected and constrained to different clock regions, you must manually insert a clock buffer and set a CLOCK_DEDICATED_ROUTE constraint on the net connected to the MMCM/XPLL/DPLL.

  • On a GT*_QUAD or IBUFDS_GT* cell

    The BUFG_GTs driven by the cell are placed in the same clock region.

AMD does not recommended using LOC constraints on the clock buffer cells. This method forces the clock onto a specific track ID, which can result in placement that cannot be legally routed. Only use LOC constraints to place high fanout clock buffers in Versal devices when you understand the entire clock tree of the design and when placement is consistent in the design. Even after taking these precautions, collisions might occur during implementation due to design or constraint changes.