Running Synthesis - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Synthesis takes in RTL and timing constraints and generates an optimized netlist that is functionally equivalent to the RTL. In general, the synthesis tool can take any legal RTL and create the logic for it. Synthesis requires realistic timing constraints.

Note: If you created your design using the Vivado IP integrator and your IP is set up within the BD file, the Vivado tools automatically run synthesis when you implement the BD file.

For additional information about synthesis, refer to the following resources:

Note: For more information on timing constraints, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).