Revision History - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

The following table shows the revision history for this document.

Section Revision Summary
11/15/2023 Version 2023.2
System Design Types Added AIE-ML link to table.
Design Planning Considerations for Dynamic Function eXchange Updated description.
Design Planning Considerations for DFX-based Vitis Acceleration Platform Development Updated #5 Minimal implementation description.
Design Planning Considerations for AI Engine and Programmable Logic Integration Added new section.
Performance/Power Trade-Off for Block RAMs Updated figure description.
Versal Device Clocking Updated figure and added clock routing notes.
Multi-Clock Buffer (MBUFG) Updated code block.
Using the CLOCK_ROUTE_GUIDE Constraint Updated CLOCK_ROUTE_GUIDE description.
Using the IMUX Register Constraint Added new section.
Floorplanning Constraints for Dynamic Function eXchange Added clocking description.
Using Incremental Implementation Flows Removed twofold description.
05/24/2023 Version 2023.1
Document title Changed title to Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).
System Design Types Added HBM.
Design Planning Considerations for the Traditional Design Flow Added design flow figure.
Design Planning Considerations for the Platform-Based Design Flow Added design flow figure.
Design Planning Considerations for Dynamic Function eXchange Added design flow figure and BDC-based DFX design description.
Design Planning Considerations for DFX-based Vitis Acceleration Platform Development Added DFX and non-DFX embedded platform creation description in platform setup.
Recommendations for Designing with Versal Device IP Added AM017 reference.
Recommendations for Different Versal Device Design Topologies Added CIPS and NoC description to BD design.
Design Creation with RTL Added UG899 link and description.
Clock Primitives Added AM017 reference.
Improving Fmax Guidance Added section.
Low Fanout Clocks Added BUFG_GTs description.
Using the CLOCK_ROUTE_GUIDE Constraint Added section.
USER_CLOCK_ROOT Assignment Added USER_CLOCK_ROOT clarification.
Synchronous CDC Added CDC path input/output clocks note.
NoC Considerations Added SSI technology description.
Designing with HBM Devices Added chapter.
Incremental Synthesis Updated to 50000 instances.
References Added AM017 reference.