Resets - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Resets are one of the more common and important control signals to take into account and limit in your design. Resets can significantly impact your design's maximum clock frequency, area, and power.

Inferred synchronous code might result in resources such as:

  • LUTs
  • Registers
  • SRLs
  • Block or LUT memory
  • DSP58 registers

The choice and use of resets can affect the selection of these components, resulting in less optimal resources for a given design. A misplaced reset on an array can mean the difference between inferring one block RAM, or inferring several thousand registers.