Reset and Clock Enable Precedence - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

In AMD devices, all registers are built to have set/reset take precedence over clock enable, whether an asynchronous or synchronous set/reset is described. In order to obtain the most optimal result, AMD recommends that you always code the set/reset before the enable (if deemed necessary) in the if/else constructs within a synchronous block. Coding a clock enable first forces the reset into the data path and creates additional logic.