Relaxing the Setup Requirement While Keeping Hold Unchanged - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

This occurs when the source and destination sequential cells are controlled by a clock enable signal that activates the clock every N cycles. The following example has a clock enable active every three cycles, with the same clock for both startpoint and endpoint:

Figure 1. Enabled Flops with Same Clock Signal

Figure 2. Timing Diagram for Setup/Hold Check


set_multicycle_path -from [get_pins REGA/C] -to [get_pins REGB/D] -setup 3
set_multicycle_path -from [get_pins REGA/C] -to [get_pins REGB/D] -hold 2
Figure 3. Setup/Hold Checks Modified After Multicycle Specification

Note: With the first command, as the setup capture edge moved to the third edge (that is, by two cycles from its default position), the hold edge also moved by two cycles. The second command is for bringing the hold edge back to its original location by moving it again by two cycles (in the reverse direction).

For more information on other common multicycle path scenarios, such as phase shift and multicycle paths between synchronous clocks, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).

Important: When the clock phase shift does not modify the clock waveform but is instead included in the insertion delay of the clock modifying block, you do not need to add a setup-only multicycle path to properly time the path from or to the clock. For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).