Recommendations for Different Versal Device Design Topologies - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

Following are the main design topologies for Versal devices:

  • RTL as top
  • BD as top

All Versal designs include some portion of the design in a block diagram because the CIPS and the NoC IP must be configured using a block design (BD). RTL as top and BD as top refer to how the block design is incorporated into the larger design. In an RTL as top design, the block diagram portion of the design is generated and stitched as a submodule into the rest of the RTL hierarchy. The design is not limited to a single BD in the RTL hierarchy. For example, the CIPS and the NoC can reside on one BD and transceivers can be on a second BD. These designs can be compiled independently and can both be stitched as a submodule into the rest of the RTL hierarchy. This provides you with some flexibility in how you partition your design.

In a BD as top design, the block diagram stitches together all of the design sources. These sources can be packaged and added to the block design as IP, or they can be referenced using RTL module referencing. Additional block designs can be incorporated into the top-level design using block design containers (BDCs).

The most significant impact the design topology has on the overall project is the interaction between the hardware and software. When a BD as top design topology is used, all the information related to how the software must interact with the hardware is passed seamlessly through the hardware hand-off file. RTL does not yet provide a similar level of transparency. Following are recommendations for when to use each design topology:

  • RTL as top is recommended if you are comfortable manually creating the device tree and installing drivers for the design peripherals.
  • BD as top is recommended if you want a seamless hardware hand-off.