Pushing the Logic from the Control Pin to the Data Pin - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

During analysis of critical paths, you might find multiple paths ending at control pins. You must analyze these paths to determine if there is a way to push the logic into the datapath without incurring penalties, such as extra logic levels. There is less delay in a path to the D pin than CE/R/S pins given the same levels of logic because there is a direct connection from the output of the last LUT to the D input of the FF. The following coding examples show how to push the logic from the control pin to the data pin of a register.

In the following example, the enable pin of dout_reg[0] has two logic levels, and the data pin has zero logic levels. In this situation, you can improve timing by moving the enable logic to the D pin by setting the EXTRACT_ENABLE attribute to "no" on the dout register definition in the RTL file.

Figure 1. Critical Path Ending at Control Pin (Enable) of a Register

The following example shows how to separate the combinational and sequential logic and map the complete logic in to the datapath. This pushes the logic into the D pin, which still has two logic levels.

You can achieve the same structure by setting the EXTRACT_ENABLE attribute to “no.” For more information on the EXTRACT_ENABLE attribute, see this link in the Vivado Design Suite User Guide: Synthesis (UG901).

Figure 2. Critical Path Ending at Data Pin of a Register (Disabling Enable Extraction)