Platform-Based Design Flow Best Practices - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

AMD recommends keeping the platform portion of your design to a minimum. For example, limit the RTL in the platform to the I/O only, and package functional RTL as a kernel. Minimizing the amount of logic in the platform reduces the overall number of platform iterations required to complete the design.

In general, AMD recommends handling computational or algorithmic logic blocks as kernels and keeping the following blocks in the platform:

  • AI Engine
  • NoC
  • CIPS
  • I/O blocks (external pins, MIPI, PHY, etc.) and related IP (DMA for PCIe® , MAC for Ethernet, etc.)

The following table shows the recommended placement of each logic type, whether in the platform or in the kernel.

Table 1. Best Practices for Platform Partitioning
Logic Platform Kernel
AI Engine Only in platform Not supported
NoC Only in platform Not supported
Hard processors (PS8, CIPS) Only in platform Not supported
Soft processors ( MicroBlaze™ processors) Preferred in platform Acceptable as kernel
I/O block (external pins, MIPI, PHY, etc.) Only in platform Not supported
IP requiring Linux drivers and software stacks (VPSS, Ethernet MAC, DMA for PCIe, etc.) Only in platform Not supported
HLS IP with AXI interfaces Acceptable in platform Preferred as kernel
RTL IP with AXI interfaces Acceptable in platform Preferred as kernel
IP with non-AXI interfaces Preferred in platform Acceptable as kernel
Note: For more information, see this link in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
Vitis libraries Acceptable in platform Preferred as kernel