Packaged Block Designs - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-11-15
Version
2023.2 English

You can package block design sources within the current Vivado project as a packaged IP for inclusion in a user IP repository.

Following is important information to note when using packaged BDs:

  • There is no view or modification capability from the top BD.
  • Packaging a BD with BDC is not supported.
  • Packaged BDs lose BD boundary properties and metadata (e.g., FREQ_HZ, X_INTERFACE_* attributes, etc.). To retain this information, the information must be present in the BD wrapper file or copied into the top source file of the IP package.
  • Packaging a BD is a snapshot of the block design. After packaging, the BD is a static IP and is not an editable or dynamic block design.
  • Packaging a BD with RTL module references is supported. However, packaging a BD with block design containers is not supported.
  • Packaging a BD that includes CIPS or NoC IP is not allowed.
  • SmartConnect and AXI Interconnect address information is static within a packaged IP.

The following figure shows the design hierarchy for a user-packaged block design that contains an RTL module reference and AMD IP.‚Äč

Figure 1. Packaged Block Design Hierarchy