NoC Considerations - 2023.2 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2023.2 English

SSI technology requires special attention during NoC planning. Familiarize yourself with the SSI technology requirements and recommendations.

To optimize performance when designing with SSI technology devices, partition the design using floorplanning techniques to target specific SLRs, keeping the utilization of each SLR within guidelines. Attempt to reduce the number of critical signals crossing SLR boundaries. This also involves proper planning of the I/O interfaces, clocks, and logic associated with the floorplan.

The NoC compiler does not consider location constraints when run within the Vivado IP integrator. After the post-synthesis is open in memory, you can floorplan the NoC interface locations to optimal SLR and refresh the NoC solution in the Vivado IDE. As the distance between NMU to NSU increases, latency can become a challenge that must be assessed and addressed early in the design cycle.

To optimize power when designing with SSI technology devices, reduce SLR crossings and constrain routes to stay in one VNoC column.

When assigning logic to Pblocks with Versal adaptive SoC SSI technology devices, you might need to perform NoC design planning to achieve optimal and consistent results throughout your design process. When performing NoC design planning, consider the following:

  • When using SLR-level Pblocks in the implementation tools, consider constraining the NoC NMU/NSU in the Vivado IP integrator to match the implementation results.
  • For NoC paths that begin or end at the DDR memory controller or PS, consider placing these paths in SLR0 to minimize latency.
  • For NoC paths that do not begin or end at the DDR memory controller or PS, consider completely constraining these paths within SLRs (other than SLR0).
  • Instead of pipelining across multiple SLRs using the AXI register slice, consider using the NoC.

In the following example, the PL-NoC paths highlighted in purple interface with the DDR memory controller and are constrained to SLR0 in the IP integrator. The NoC paths highlighted in pink are PL-NoC paths that are constrained to SLR1 in the IP integrator.

Figure 1. SLR-Level Design Planning in IP Integrator